“Electrostatic Discharge” (ESD) describes the processes and effects when electrical charges are equalized between two differently charged components. If the latter come into contact with one another, positive and negative charges are exchanged, and this may give rise to damage in an electrical circuit.
In an integrated circuit, an upper operating potential VDD and lower operating potential VSS are provided, between which provision is made of protection mechanisms for avoiding damage on account of ESD.
ESD, that is to say electrostatic discharges, are often the cause of damage to or destruction of an integrated circuit and thus cause high financial damage. The development of MOS technology (metal oxide semiconductor) in microelectronics has been accompanied by a miniaturization of the semiconductor components at increasingly high clock rates. This results in a rising sensitivity towards ESD pulses, that is to say high voltage and current spikes of such clock signals. Semiconductor components under ESD stress can cause errors in an integrated circuit. ESD can lead to a total failure of or damage to the component. Therefore, protection against electrostatic discharges (ESD protection) is important nowadays in all areas of microelectronics.
ESD protection in radiofrequency circuitry applications is a difficult technical problem, since the high parasitic capacitance of ESD protection elements inherently greatly restricts the maximum operating frequency that can be achieved for the circuit. Such ESD protection elements are, for example, a diode, a thyristor or a grounded n-MOS component (that is to say an n-MOS field effect transistor with a gate terminal at the electrical ground potential). Smaller ESD protection elements would enable higher frequencies, but do not sufficiently satisfy the functionality as ESD protection, that is to say are not sufficiently able to dissipate ESD currents.
A description is given below, referring to FIG. 1, of a circuit arrangement 100 with ESD protection in accordance with the prior art.
In the case of the circuit arrangement 100, an input signal can be provided at a signal input pad 101 and be fed to an input/output circuit 102. In order to supply the circuit arrangement 100 with electrical energy, a supply potential 103 VDD is provided, and an electrical ground potential 104 GND. A first ESD protection element 105 is provided between the signal input pad 101 and the supply potential 103 VDD. Furthermore, a second ESD protection element 106 is provided between the signal input pad 101 and the electrical ground potential 104.
Furthermore, FIG. 1 shows a circuit arrangement 110, which has, in addition to the components of the circuit arrangement 100, a nonreactive resistor 111 between the signal input pad 101 and the input/output circuit 102.
FIG. 1 clearly shows circuit arrangements 100, 110 having protection against high voltages through the provision of the ESD protection elements 105, 106, since the latter electrically decouple the supply potential 103 VDD from the ground potential 104 GND.
In the case of a large electric current intensity, the ESD elements 105, 106 have to be sufficiently large. In radiofrequency applications, however, large ESD elements lead to an undesirable large parasitic capacitance.
Approaches for ESD protection circuit arrangements for radiofrequency circuits are disclosed in (1) Ming-Dou Ker at al., EOS/ESD-Symp. Proceedings 2003, pages 204-213, (2) Vassilev, V et al., EOS/ESD-Symp. Proceedings 2003, pages 195-203, (3) Hyvonen et al., EOS/ESD-Symp. Proceedings 2003, pages 188-194, (4) Galai, S, Razavi, B “Broadband ESD Protection Circuits in CMOS-Technology”, Proceedings ISSCC 2003, Paper 10.5, (5) Leroux, P, Steyaert, M “A high performance 5.2 GHz LNA with an on-chip inductor to provide EDS-protection”, IEE Electronics Letters, Volume 37, No. 1, pages 467-469, March 2001, (6) Leroux, P, Janssens, J, Steyaert, M “A 0.8 dB NF ESD-protected 9 mW CMOS LNA”, ISSCC Dig. Tech. Papers, Volume 26, pages 410-411, 2001, (7) Mahdavi, S, Abidi, A “Fully integrated 2.2-mW CMOS Front End for a 900-MHz Wireless Receiver”, IEEE JSSC, 05/2002, and (8) Liebermann, T, Tiebout, M “A Low Phasenoise, Differentially Tuned, 1.8 GHz Power VCO with an ESD-compatible 14 dBm Output Stage in Standard Digital CMOS”, ESSCIRC Proceedings, Villach, 09/2001.
The approach disclosed in Leroux, P, Steyaert, M “A high performance 5.2 GHz LNA with an on-chip inductor to provide EDS-protection”, IEE Electronics Letters, Volume 37, No. 1, pages 467-469, March 2001, Leroux, P, Janssens, J, Steyaert, M “A 0.8 dB NF ESD-protected 9 mW CMOS LNA”, ISSCC Dig. Tech. Papers, Volume 26, pages 410-411, 2001, and Mahdavi, S, Abidi, A “Fully integrated 2.2-mW CMOS Front End for a 900-MHz Wireless Receiver”, IEEE JSSC, 05/2002, essentially consists in using smaller ESD protection elements.
FIG. 2 shows an ESD protection circuit 200 such as is disclosed in Mahdavi, S, Abidi, A “Fully integrated 2.2-mW CMOS Front End for a 900-MHz Wireless Receiver”, IEEE JSSC, 05/2002.
FIG. 3 shows an ESD protection circuit arrangement 300 disclosed in Leroux, P, Janssens, J, Steyaert, M “A 0.8 dB NF ESD-protected 9 mW CMOS LNA”, ISSCC Dig. Tech. Papers, Volume 26, pages 410-411, 2001, in the case of which arrangement the ESD protection is realized by means of a first ESD protection diode 201 and by means of a second ESD protection diode 302.
The approaches in accordance with Leroux, P, Steyaert, M “A high performance 5.2 GHz LNA with an on-chip inductor to provide EDS-protection”, IEE Electronics Letters, Volume 37, No. 1, pages 467-469, March 2001, Leroux, P, Janssens, J, Steyaert, M “A 0.8 dB NF ESD-protected 9 mW CMOS LNA”, ISSCC Dig. Tech. Papers, Volume 26, pages 410-411, 2001, and Mahdavi, S, Abidi, A “Fully integrated 2.2-mW CMOS Front End for a 900-MHz Wireless Receiver”, IEEE JSSC, 05/2002, have the disadvantage, however, that they usually have only low ESD strength, and that the range of processable radio frequencies with which the circuit arrangements can be operated is restricted. At higher frequencies such as 5 GHz or 17 GHz such as are used for WLAN systems (“wireless local area network”) these approaches are thus only poorly suitable or no longer suitable at all.
An alternative approach in accordance with Ming-Dou Ker at al., EOS/ESD-Symp. Proceedings 2003, pages 204-213, Vassilev, V et al., EOS/ESD-Symp. Proceedings 2003, pages 195-203, Hyvonen et al., EOS/ESD-Symp. Proceedings 2003, pages 188-194, and Galai, S, Razavi, B “Broadband ESD Protection Circuits in CMOS-Technology”, Proceedings ISSCC 2003, Paper 10.5essentially consists in decoupling the ESD protection elements using LC resonant circuits realized on-chip, or in tuning the capacitance of each ESD element in an LC resonant circuit.
The ESD protection circuit arrangement 400 shown in FIG. 4 represents a solution such as is disclosed in Galai, S, Razavi, B “Broadband ESD Protection Circuits in CMOS-Technology”, Proceedings ISSCC 2003, Paper 10.5. The ESD protection circuit arrangement 400 is provided with a first ESD protection subcircuit 401 and a second ESD protection subcircuit 402, an ESD capacitance 403 representing a (parasitic) capacitance of the ESD protection elements 401, 402.
What is disadvantageous about the approach in accordance with Ming-Dou Ker at al., EOS/ESD-Symp. Proceedings 2003, pages 204-213, Vassilev, V et al., EOS/ESD-Symp. Proceedings 2003, pages 195-203, Hyvonen et al., EOS/ESD-Symp. Proceedings 2003, pages 188-194, and Galai, S, Razavi, B “Broadband ESD Protection Circuits in CMOS-Technologyis the high area requirement of the integrated inductances.
In the case of the ESD protection circuit arrangement 500 disclosed in Liebermann, T, Tiebout, M “A Low Phasenoise, Differentially Tuned, 1.8 GHz Power VCO with an ESD-compatible 14 dBm Output Stage in Standard Digital CMOS”, ESSCIRC Proceedings, Villach, 09/2001, which is shown in FIG. 5, an inductance is used instead of traditional ESD protection elements. ESD protection is clearly achieved by means of the standard ESD protection elements coupled to the supply voltage.
Consequently, the ESD protection circuit arrangement 500 is provided with a first inductance 501 and a second inductance 502, but also a capacitance 503. Furthermore, a plurality of signal inputs 101 and a plurality of signal outputs 102 are provided.
The problem of effective ESD protection is particularly pronounced in the context of a differential circuit in the case of an ESD discharge between two differential radiofrequency input/output pins (RF I/O pins). Conventional ESD protection of the radiofrequency input/output pins against local supply potentials leads to particularly high voltage drops across an ESD protection path.
A description is given below, referring to FIG. 6, of a circuit arrangement 600 in accordance with the prior art, which reveals the particular jeopardization of a differential RF input circuit in the case of one ESD discharge between two differential RF pins (IN and IP).
The circuit arrangement 600 contains a first signal input pad 601 (IN) and a second signal input pad 602 (IP) between which a differential input signal can be provided. A differential output signal can be provided between a first signal output 603 (ON) and a second signal output signal 604 (OP). The first signal input pad 601 is coupled to the gate region of a first n-MOS field effect transistor 605, the first source/drain region of which is coupled to a current source 607 and the second source/drain region of which is coupled to the first signal output 603. The second signal input pad 602 is coupled to the gate region of a second n-MOS field effect transistor 606, the first source/drain region of which is coupled to the current source 607 and the second source/drain region of which is coupled to the second signal output 604. A second terminal of the current source 607 is brought to the ground potential 104 VSS. Three ESD protection paths are formed between the supply potential 103 VDD and the ground potential 104 VSS. A first ESD protection path comprises a first ESD protection diode 608 and a second ESD protection diode 609. A second ESD protection path comprises a third ESD protection diode 610 and a fourth ESD protection diode 611. A third ESD protection path comprises an ESD protection element 612, which may be a thyristor for example. As shown by way of example in FIG. 6, in the event of a positive discharge from the RF input pin IN 601 with respect to the second RF input pin IP 602, the ESD current is passed via three protection elements in series (protection diodes 608, 609 at IN, protection element 612 between VDD and VSS, protection diodes 610, 611 at IP). The high voltage drop arising in this case may lead to the breakdown of the two gate insulating layers of the input transistors 605, 606, that is to say to an undesirable current flow between the gate regions of the transistors 605, 606, and may thus destroy the circuit arrangement 600. Conventionally, this problem can only be combated by inserting additional protection elements, which would degrade the performance of the circuit on account of the additional capacitance per unit length.
DE 102 39 230 A1 discloses a radiofrequency semiconductor device in which an ESD protection circuit is connected to a node forming a branch junction of a radiofrequency signal input/output line, one end of the radiofrequency signal input/output line being connected to a radiofrequency input/output pad, the other end of the radiofrequency input/output line being connected to an internal circuit, and a DC blocking capacitor being connected in series between the node and the internal circuit.